1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and particularly to a method of fabricating a memory array using a self-aligned contact (SAC) technique.
2. Description of the Related Art
In the fabrication of a semiconductor device, an exemplary application of the self-aligned contact (SAC) technique is to form a contact between a pair of adjacent wordlines (gate structures of the field-effect transistors) in a memory array so as to electrically connect a source/drain region (junction region) of the transistor to a bitline.
A typical method for forming a self-aligned contact according to the prior art will be explained with reference to FIGS. 1(a) and 1(b).
First, as shown in FIG. 1(a), gate structures 101 for transistors are provided on a substrate 100, and a source/drain region (junction region) 110 is formed in the substrate by using an ion implantation technique. Typically, each of the gate structures 101 includes a polysilicon layer 106 and a tungsten silicide layer 104 atop the polysilicon layer 106. Further, a cap layer 102 is formed to cap the tungsten silicide layer 104, and two spacers 108 are respectively provided along both side walls of the stack structure formed by the layers 102, 104 and 106. The cap layer 102 and the spacers 108 are all made of silicon nitride, which not only prevents the gate from being etched but also acts as a insulator between the gate and a contact.
Next, a thick oxide insulative material, for example, borophosphosilicate glass (BPSG), is filled in the memory array region, forming an oxide layer (insulating layer) 112.
Then, as shown in FIG. 1(b), a photoresist layer is coated on the surface of the oxide layer 112 to form a mask 114 defined with a predetermined pattern exposing the region where the contact is to be formed. Later, the oxide layer 112 is etched through to the junction region 110 in the substrate 100 to form a contact hole 116 by using an etch process highly selective for the oxide relative to the nitride, i.e., an etch process in which an oxide etch rate is much greater than a nitride etch rate.
Finally, metallic contact material is filled into the contact hole 116 to form a contact for an electric connection between the junction region and a bitline.
Although the cap layer 102 and the spacer 108 will be exposed to the enchant during the formation of the contact hole 115, it is etched very slowly since the SAC oxide etch is highly selective to nitride. Therefore, the SAC technique is advantageous in that it allows the dimension of the contact hole to be wider than the width between two adjacent gate structures and that it allows the mask 114 for exposing the contact hole to be less precisely aligned.
However, in a semiconductor process having a feature size of 70 nm or less, the following problems will occur when adopting the conventional SAC technique.
First, during the formation of the contact hole, the corner portion of the nitride (cap layer 102 and spacer 108), which has a geometric shape apt to be etched, is exposed to the etchant for a long time since the oxide layer to be etched through has a relative large depth. Therefore, it is difficult to prevent over-etching of the nitride. This causes exposure of the gate to the contact, leading to short-circuiting between the wordline and the bitline.
Second, the etchant used in the formation of the contact hole also erodes the junction region in the substrate. When the feature size is reduced, junction depth becomes shallow; for example, for the 70 nm process, the junction depth is only about 200 Å. Therefore, loss of the silicon substrate results in a considerable junction leakage.